Semiconductor devices
US11398495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a peripheral circuit region on a first substrate and including circuit devices, a memory cell region on a second substrate overlaid on the first substrate, with the memory cell region including gate electrodes stacked to be spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and channel structures which extend vertically on the second substrate and penetrate through the gate electrodes. The channel structures may include a channel layer. The semiconductor device includes a through-wiring region with through-contact plugs that extend in the first direction and that electrically connect the memory cell region and the peripheral circuit region to each other, with the through-wiring region including an insulating region that surrounds the through-contact plugs. The through-wiring region further includes dummy channel structures regularly arranged throughout the through-wiring region and which include the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.