Array substrate, display panel, and manufacturing method of the array substrate
US11398507B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes an insulation layer and one or more stepped holes each penetrating through the insulation layer in a direction perpendicular to the insulation layer. Each stepped hole includes a first hole and a second hole under the first hole, a radius of the first hole at a bottom is a first radius, a radius of the second hole at a top is a second radius which is substantially smaller than the first radius, and a difference between the first radius and the second radius is 0.2 μm to 0.6 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.