Delay locked loop circuit
US11398824B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Sep 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit includes: a variable delay line configured to delay an initial clock signal to generate a delayed clock signal; and a control circuit connected to the variable delay line, configured to control the variable delay line to perform delay adjustment of a first mode and further configured to perform delay adjustment of a second mode on the variable delay line when the delayed clock signal satisfies a preset condition. A step value of each delay adjustment of the first mode is a first step value, a step value of each delay adjustment of the second mode is a second step value, and the second step value is greater than the first step value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.