Receiving device, control method of receiving device, and memory controller
US11398825B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2021 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Aug 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/187
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiving device includes a phase-locked loop (PLL) circuit having a current control oscillator, a phase detector, an integral path, and a proportional path. The current control oscillator can generate an oscillation clock based on a first and second current. The phase detector can acquire a phase detection result based on the oscillation clock and a received signal. The integral path can generate the first current based on an integrated value of the phase detection results and supply the first current to the current control oscillator. The proportional path includes a digital-to-current converter to generate the second current based on the phase detection result and supply the second current to the current control oscillator. The receiving device includes a controller configured to adjust the second current based on frequency-current characteristics of the current control oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.