Phase-locked loop with phase noise cancellation
US11398827B1 · kind B1 · utility
2Cited by
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18Claims
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Key dates
| Filing date | Aug 6, 2021 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes a first phase-locked loop (PLL), a converter circuit, and a second PLL. The first PLL generates an oscillating signal based on a reference signal and outputs a noise signal indicating a noise component of the oscillating signal. The converter circuit produces an electrical signal based on the noise signal. The second PLL receives the electrical signal from the converter circuit at a loop filter of the second PLL and generates a clock signal based on the oscillating signal and the electrical signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.