Interference mitigation in high speed ethernet communication networks
US11398931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2021 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Jan 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.