Method and apparatus for debugging, and system on chip
US11403206B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | May 10, 2019 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Jan 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method and an apparatus for debugging, and a system on chip. The method for debugging includes: a component to be debugged receives a debugging instruction from a controller, and the component to be debugged performs debugging operation according to the debugging instruction and configuration of a state machine inside the component to be debugged. Then an SW level debugging operation of component on system on chip can be achieved, which improves the debugging efficiency of these components with large amounts of data flow on system on chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.