Memory system and semiconductor storage device configured to discharge word line during abrupt power interrupt
US11404101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2021 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Jan 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a semiconductor storage device, a power supply circuit that generates a first power, and a memory controller that operates based on the first power and transmits a command to the semiconductor storage device. The semiconductor storage device includes a first terminal, a second terminal, a word line, a first circuit, and a second circuit. The first power is input to the first terminal. A second power that can be used even after a voltage of the first terminal decreases is input to the second terminal. The word line is connected to a control gate of a memory cell transistor. The first circuit applies a voltage according to the command to the word line based on the first power input to the first terminal. The second circuit discharges charges of the word line by using the second power input to the second terminal when a voltage of the first terminal decreases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.