Write disturb refresh rate reduction using write history buffer
US11404105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Dec 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.