Semiconductor structure and forming method thereof
US11404273B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 22, 2021 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure and a forming method thereof. One form of a forming method includes: providing a base; forming a plurality of discrete mandrel layers on the base, where an extending direction of the mandrel layers is a first direction, and a direction perpendicular to the first direction is a second direction; forming a plurality of spacer layers covering side walls of the mandrel layers; forming a pattern transfer layer on the base, where the pattern transfer layer covers side walls of the spacer layers; forming a first trench in the pattern transfer layer between adjacent spacer layers in the second direction; removing a mandrel layer to form a second trench after the first trench is formed; and etching the base along the first trench and the second trench to form a target pattern by using the pattern transfer layer and the spacer layer as a mask. In the present disclosure, the accuracy of the pattern transfer is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.