Semiconductor memory device and method of fabricating same
US11404538B2 · kind B2 · utility
2Cited by
9References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 18, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Aug 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7624
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.