Method for forming MTJS with lithography-variation independent critical dimension
US11404633B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Mar 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F10/329
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.