Duty adjustment circuit, and delay locked loop circuit and semiconductor memory device including the same
US11405029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2021 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.