Directed acyclic graph template for data pipeline
US11405312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Oct 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/54
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computing system is provided, including a processor configured to receive a directed acyclic graph (DAG) template specifying a data pipeline of a plurality of processing stages. For each processing stage, the processor may be further configured to select a respective processing device of a plurality of communicatively linked processing devices. The processor may be further configured to determine a routing sequence between the plurality of processing devices according to the DAG template. The processor may be further configured to transmit a plurality of input packets encoding the plurality of processing stages to the respective processing devices selected for the processing stages as specified by the routing sequence. In response to transmitting the plurality of input packets, the processor may be further configured to receive, from a processing device of the plurality of processing devices, one or more output packets encoding a processing result of the data pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.