Identifying random bits in control data packets
US11407218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2019 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Jul 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/1285
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.