Hardware random forest: low latency, fully reconfigurable ensemble classification
US11409286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Feb 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.