Delay monitoring scheme for critical path timing margin
US11409323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2019 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Sep 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*σmax; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.