System and methods for hardware-software cooperative pipeline error detection
US11409597B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Mar 6, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.