Tags and data for caches
US11409659B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2021 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Apr 2, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.