Artificial reality system having multi-bank, multi-port distributed shared memory
US11409671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Jul 22, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.