Semiconductor device having electrode pads arranged between groups of external electrodes
US11410900B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Apr 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.