Gate structure, method of forming the same, and semiconductor device having the same
US11411112B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | May 31, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | May 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.