Variable resistance memory device and method of fabricating the same
US11411179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/881
Abstract
A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.