Protection for ethernet physical layer
US11416332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments include an Ethernet PHY device comprising a serial communication interface adapted to be coupled to a microcontroller, a register set having registers, and a checksum generator circuit coupled to the register set and configured to calculate a current checksum. The embodiment also includes a checksum register that is coupled to the checksum generator and is configured to store the current checksum. It further includes a checksum checker that is coupled to the checksum generator, the checksum register and the microcontroller, and is configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller. The embodiment also includes a trigger circuit coupled to the checksum generator configured to send a checksum start signal to the checksum generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.