Semiconductor memory devices and memory systems with enhanced error detection and correction
US11416335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Dec 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.