System with cache-coherent memory and server-linking switch
US11416431B2 · kind B2 · utility
5Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Sep 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.