Optimized allocation of functions in hybrid motor controller implementations

US11416663B2 · kind B2 · utility

Assignee

• Hamilton Sundstrand Corporation (HSC) · US

Inventors

• Ashish Vijay · Gothan, IN
• Sesh Mohan Rao · Bengaluru, IN
• Rajeeva Gopala Krishna · Survanagiri, IN
• Shardul Shrinivas Bapat · Survanagiri, IN
• Rajagopal Srinivasan · Pittsburgh, US
• Manish Kumar · Frisco, US

Key dates

• Filing date: Dec 11, 2019
• Grant date: Aug 16, 2022
• Expiry date: Oct 19, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2213/0038
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system for controlling a motor with a plurality of motor control functions including at least a current control loop and a velocity control loop. The system includes one of a hybrid Digital Signal Processor (DSP)-Field Programmable Gate Array (FPGA) architecture having an integral DSP and an integral FPGA or a System on a Chip (SoC) architecture having a Microcontroller Sub-System (MSS) and an FPGA fabric. The current control loop function is assigned to the integral FPGA for the hybrid DSP-FPGA architecture, and at least the velocity control loop function is assigned to the DSP the hybrid DSP-FPGA architecture. Alternatively, the current control loop function is assigned the FPGA fabric of the SoC architecture, and at least the velocity control loop function is assigned to the MSS of the SoC architecture.