Anti-aliasing two-dimensional vector graphics using a multi-vertex buffer
US11417058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Sep 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T17/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and non-transitory computer readable storage media are disclosed for utilizing a central processing unit to generate a compressed multi-vertex buffer to include rendering data from tessellated geometry of a two-dimensional vector graphic for rendering the two-dimensional vector graphic via a GPU rendering pipeline. For example, the disclosed system generates an expanded geometry for control triangles within the tessellated geometry based on an anti-aliasing direction. The disclosed system generates multi-vertex buffer entries including vertex locations and visual attributes (e.g., color, primitive type, anti-aliasing direction, stroke width) of the vector paths corresponding to each triangle in the tessellated geometry. Furthermore, the disclosed system renders the two-dimensional vector graphic by passing the rendering data stored in the compressed multi-vertex buffer to the graphics processing unit in a manner that the graphics processing unit is able to process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.