Patent · US Active

Method of manufacturing semiconductor package

US11417559B2 · kind B2 · utility

0Cited by
5References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 4, 2020
Grant dateAug 16, 2022
Priority date—
Expiry dateDec 4, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2224/12105
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

To manufacture a semiconductor package, a package intermediate structure having an element area and a dummy area is formed. A carrier substrate including an adhesion layer is formed. The adhesion layer includes a first area with a first adhesion strength and a second area with a second adhesion strength that is different from the first adhesion strength. The package intermediate structure is supported by the carrier substrate so that the element area is adjacent the first area and the dummy area is adjacent the second area. The package intermediate structure is processed while the package intermediate structure is supported by the carrier substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.