Dopant profile control in gate structures for semiconductor devices
US11417571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Jun 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.