Method for manufacturing semiconductor structure
US11417628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Sep 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1431
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.