Semiconductor package
US11417631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2019 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | May 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a first semiconductor package including: a first frame having a first through portion, a first semiconductor chip in the first through portion and having a first surface on which a first connection pad is disposed and a second surface on which a second connection pad is disposed, and a through via connected to the second connection pad, a first connection structure on the first surface and including a first redistribution layer, and a backside redistribution layer on the second surface; and a second semiconductor package on the first semiconductor package and including: a second connection structure including a second redistribution layer, a second frame on the second connection structure and having a second through portion, and a second semiconductor chip in a second through portion and having a third surface on which a third connection pad is disposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.