Differential signal offset adjustment circuit and differential system
US11418159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Jan 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45612
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors. A fifth resistor is coupled between the third and fourth current sources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.