Digital clock generation and variation control circuitry
US11418198B2 · kind B2 · utility
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13References
28Claims
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Key dates
| Filing date | Aug 28, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Aug 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.