Computational accelerator for packet payload operations
US11418454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Mar 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/326
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.