Patent · US Active

System and method for testing critical components on system-on-chip

US11422185B2 · kind B2 · utility

0Cited by

11References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Neha Srivastava · New Delhi, IN
Garima Sharda · Ghaziabad, IN

Key dates

Filing date	Jun 30, 2020
Grant date	Aug 23, 2022
Priority date	—
Expiry date	Mar 10, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3187
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.