Identifying fixed bits of a bitstring format
US11423247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Feb 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for identifying fixed bits of a bitstring format. One or more processors are configured to generate a first bitstring having respective first bit values that have a first satisfiability state and generate a second bitstring having respective second bit values that have a second satisfiability state. The one or more processors are configured to identify first potential free bits having respective first common values and generate a third bitstring having first potential free bits with the respective first common values and third remaining bits. The one or more processors are configured to identify second potential free bits having respective second common values and identify a fixed bit that is not included in the first potential free bits and is not included in the second potential free bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.