Wafer-level process for curving a set of electronic chips

US11424286B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Bertrand Chambion · Chambéry, FR
• Jean-Philippe Colonna · Grenoble, FR

Key dates

• Filing date: Jul 24, 2020
• Grant date: Aug 23, 2022
• Expiry date: Feb 23, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10H29/142

Abstract

A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.