Semiconductor device
US11424341B2 · kind B2 · utility
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20Claims
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Assignee
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Key dates
| Filing date | Jul 24, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Jul 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.