Analog lock detector for a phase lock loop
US11424749B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog lock detector for a phase lock loop includes a detector, a logic gate, a delay circuit, and a guard gate inverter. The detector outputs up and down signals relating synthesized and reference frequencies. The logic gate outputs an initial lock signal combining the up and down signals. While the synthesized and reference frequencies are locked, the initial lock signal has a steady state except during brief intervals. The delay circuit outputs a delayed lock signal that time delays the initial lock signal by a delay amount, which matches a maximum allowed duration of the brief intervals while locked. A guard gate inverter outputs a final lock signal that combines the initial lock signal and the delayed lock signal. The final lock signal has the steady state indicating when the synthesized frequency is locked to the reference frequency, but without the brief intervals of deviation from the steady state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.