Successive-approximation-register (SAR) analog-to-digital converter (ADC) timing calibration
US11424753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | May 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.