Noise-shaping analog-to-digital converter
US11424754B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | May 24, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | May 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Testing of the noise-shaping circuitry within a successive approximation register (“SAR”) analog-to-digital converter (“ADC”) (“SAR ADC”) to ensure it will function as expected, while also providing a method for calibrating the coefficients of the noise-shaping circuitry. Programmable/trimmable circuit component(s) can be used to calibrate the coefficient(s) of the SAR ADC. Digital logic within the SAR engine enables it to selectively skip portions of the ADC conversion process and to use voltage references rather than an analog voltage input signal in sample mode during such test/calibration modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.