Decoder for low-density parity-check codes
US11424762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Nov 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P≥PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.