Retimer with mesochronous intra-lane path controllers
US11424905B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | May 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.