Static data bus address allocation
US11424952B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Apr 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2101/627
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a data bus node integrated circuit comprising at least one static address selection terminal and a detecting circuit for detecting a state of the address selection terminal. The IC also comprises a communication circuit for data communication over a data bus. This circuit is adapted for determining a node address identifier taking the detected state of the at least one static address selection terminal into account. The detecting circuit is adapted for detecting the state of the address selection terminal by determining whether the address selection terminal is in a floating state, a power supply voltage state or a ground voltage state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.