Turn-based deadlock-free routing in a Cartesian topology
US11425027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Jan 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/508
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.