Digital linear regulator clamping method and apparatus

US11429172B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Alexander B. Uan-Zo-Li · Hillsboro, US
• Eugene Gorbatov · Hillsboro, US
• Harish Krishnamurthy · Beaverton, US
• Alexander Lyakhov · Haifa, IL
• Patrick K. Leung · Hillsboro, US
• Stephen H. Gunther · Beaverton, US
• Arik Gihon · Nesher, IL
• Khondker Ahmed · Hillsboro, US
• Philip R. Lehwalder · Hillsboro, US
• Sameer Shekhar · Portland, US
• Vishram Shriram Pandit · Kanchinakote, IN
• Nimrod Angel · Haifa, IL
• Michael Zelikson · Haifa, IL

Key dates

• Filing date: Jan 6, 2020
• Grant date: Aug 30, 2022
• Expiry date: Jan 6, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G05F1/56
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.