Data driving circuit and display apparatus with reduced power consumption
US11430363B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Sep 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data driving circuit of reduced power consumption by smoothing large voltage changes includes a shift register circuit, a first latch, a second latch, a level shift circuit, a digital-to-analog (DAC) circuit, and an output circuit. The first latch circuit samples the digital signal, the second latch circuit detects a boundary value of the sampled signal in a specified grayscale range. The boundary value of the sampled signal is compared with the boundary value of a previous sampled signal and if different from the previous boundary value, the second latch outputs a compensation control signal being effective; the output circuit sets the voltage of the data line at a specified voltage before outputting the driving voltage to the data line. A display apparatus is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.