Read integration time calibration for non-volatile storage
US11430531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Feb 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read reference levels are calibrated by calibrating integration times. An integration time is the length of time for which the charge on a sense node is allowed to change while the memory cell is being sensed. Calibrating the integration time is much faster than calibrating the reference voltage itself. This is due, in part, to reducing the number of different reference voltages that need to be applied during calibration. Calibrating the integration time may use different test integration times for a given read reference voltage, thereby reducing the number of read reference voltages. Hence, calibrating the integration time(s) is very efficient timewise. Also, power consumption may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.