Patent · US Active

Gate driving circuit

US11430532B2 · kind B2 · utility

1Cited by

2References

10Claims

0Family size

Assignee

Au Optronics Corporation · TW

Inventors

Yu-Jen Chen · Tainan, TW
Meng-Chieh Tsai · Baoshan, TW

Key dates

Filing date	Nov 11, 2020
Grant date	Aug 30, 2022
Priority date	—
Expiry date	Dec 30, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG09G2310/08
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.